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Journal > International Journal of Electrical and Computer Engineering (IJECE) > A Study of Gate Length and Source-Drain Bias on Electron Transport Properties in SiC Based MOSFETs Using Monte Carlo Method

 

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International Journal of Electrical and Computer Engineering (IJECE)
Vol 1, No 1: September 2011
A Study of Gate Length and Source-Drain Bias on Electron Transport Properties in SiC Based MOSFETs Using Monte Carlo Method
Article Info   ABSTRACT
Published date:
24 Sep 2011
 
           Ensemble Monte Carlo simulations have been carried out to investigate the effects of Gate length and different source-drain bias on the characteristics of wurtzite SiC MOSFETs. Electronic states within the conduction band valleys are represented by non-parabolic ellipsoidal valleys centred on important symmetry points of the Brillouin zone. The following scattering mechanisims, i.e, impurity, polar optical phonon, acoustic phonon, alloy and piezoelectric are inculded in the calculation. Ionized imurity scattering has been treated beyound the Born approximation using the phase-shift analysis. Two transistors with gate lengths of 200 and 400 nm are simulated. Simulations show that with a fixed channel length, when the gate length is decreased, the output drain current is increased, and therefore the transistor transconductance increases. Moreover, with increasing temperature the drain current is reduced, which results in the reduced drain barrier lowering. The simulated device geometries and doping are matched to the nominal parameters described for the experimental structures as closely as possible, and the predicted drain current and other electrical characteristics for the simulated device show much closer agreement with the available experimental data.
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