Announcement
Starting on July 4, 2018 the Indonesian Publication Index (IPI) has been acquired by the Ministry of Research Technology and Higher Education (RISTEKDIKTI) called GARUDA Garba Rujukan Digital (http://garuda.ristekdikti.go.id)
For further information email to portalgaruda@gmail.com

Thank you
Logo IPI  
Journal > International Journal of Electrical and Computer Engineering (IJECE) > Multilevel MPSoC Performance Evaluation: New ISSPT Model

 

International Journal of Electrical and Computer Engineering (IJECE)
Vol 5, No 5: October 2015
Multilevel MPSoC Performance Evaluation: New ISSPT Model
Alali, A. ( Hassan II University)
Assayad, I. ( Hassan II University)
Sadik, M. ( Hassan II University)
Article Info   ABSTRACT
Published date:
01 Oct 2015
 
To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin.
Copyrights © 2015